SERializer/DESerializer (SERDES) devices are integrated circuit (IC) transceivers that convert parallel data streams to serial data streams and vice-versa. Such devices are often used in high speed communications circuits such as Gigabit Ethernet systems, wireless network routers, fiber optic communications systems and storage applications. Some SERDES devices are capable of operating at speeds in excess of 10 Gigabits per second (Gbps).
Each SERDES transceiver typically includes (i) a transmitter portion having a parallel-to-serial converter to convert parallel data into serial data, and (ii) a receiver portion having a serial-to-parallel converter to convert serial data into parallel data. This configuration enables SERDES transceivers to convey parallel data between two points over serial streams and thus reduce the number of data paths, the number of connecting pins and the number of wires involved in the transfer.
The receiver portions of SERDES transceivers include time-dispersive channels that are susceptible to intersymbol interference (ISI). To boost the signal-to-noise ratio and the bit-error-rate (BER) of the receiver portions, manufacturers typically include Decision Feedback Equalizers (DFEs) in the receiver portions of the SERDES transceivers.
FIG. 1 shows a conventional DFE 20 which is capable of being used in high-speed SERDES technology. As shown, the DFE 20 is a nonlinear equalizer having a signal pathway 22 and a feedback filter 24. The signal pathway 22 follows a pre-emphasis stage 26 and a channel 28, and resides on the receiver side of a larger electronic circuit. The signal pathway 22 includes summation circuitry 30 and a sampler (or output) 32 which are serially connected. The feedback filter 24 includes a tapped delay line 34 formed by series-connected delay segments (or circuits) 34(2), . . . 34(n) and associated weight circuits 36(1), 36(2), . . . 36(n) (collectively, weight circuits 36). The non-linearity of the DFE 20 should be clear in FIG. 1 since the output of the sampler block 32 is required as input in a feedback loop manner through the feedback filter 24 and the summation circuit 30.
During operation, the signal pathway 22 of the DFE 20 receives an input signal 38 from the channel 28 and provides an output signal 40. The delay line 34 of the feedback filter 24 receives the output signal 40 from the sampler 32 and provides a set of delayed signals 42(1), 42(2), . . . 42(n) (collectively, delayed signals 42) to the associated weight circuits 36 in a feedback loop manner. Typically, the delay segments 34(2), . . . 34(n) are 1-bit timer delay circuits that provide 1-bit delays to the output signal 40. The weight circuits 36 then provide a set of weighted signals 44(1), 44(2), . . . 44(n) (collectively, weighted signals 44) to the summation circuitry 30 of the signal pathway 22 in response to (i) the set of delayed signals 42 and (ii) a set of decisions 46 (e.g., training from a controller).
It should be understood that the decisions 46 (i.e., a specific decision 46 for each weight circuit 36) enable the signal pathway 22 of the DFE 20 to output, as the output signal 40, a weighted sum of the values of the input signal 38 and the weighted signals 44. Such feedback-loop operation enables the DFE 20 to cancel the intersymbol interference while minimizing noise enhancement which is a typical deficiency of conventional linear equalizers.
It should be further understood that conventional Electronic Design Automation (EDA) tools are capable of modeling DFE circuits. For example, the following is a pseudo-code model for a DFE which is similar to the DFE 20 of FIG. 1.
1.Initialize all state variables2.Input bits convolute with channel and pre-emphasis function:temp1 = input © pre-emphasis © Channel3.For i = 1 : length of temp1temp2(i) = temp1(i) + FIR_filter(output(1:i−1))output(i) = Sampler(temp2(i))4.End for loopIn this pseudo-code model, the current bit value (e.g., temp 2) is a based on a previous bit value. That is, the signal from the channel into the summation circuit (e.g., see the signal 47 in FIG. 1) corresponds to temp 1, and the signal from the summation circuit entering the sampler block (e.g., see the signal 48 in FIG. 1) corresponds to temp 2. The symbol © in the above-provided pseudo-code represents a convolution operation.